Ready for Transfer

Fermilab’s SEUSS Technology

Lab(s):
Fermi National Accelerator Laboratory (FNAL)

Laboratory: Fermi National Accelerator Laboratory (Fermilab)

Technology: Single Event Upset Suppression System (SEUSS)

Opportunity: Fermilab is seeking partners to develop and license the SEUSS technology so it can reach its full market potential.

Details: Single Event Upset Suppression System (SEUSS) cells are designed to be immune to single event upsets (SEU). SEUSS can be configured as two different kinds of SEU-tolerant SR latches. One SEUSS cell emulates a cross-coupled NOR gate SR flip-flop (SEUSSNor), and the other a cross-coupled NAND gate SR flip-flop (SEUSSNand).

Benefits: There are two widely used SEU hardening techniques: tech hardening and design hardening. Tech hardening involves making changes to the fabrication of the chip to reduce SEU occurrences. These fabrication processes can cost a company billions of dollars to develop.

Design hardening is only limited by a designer’s creativity.

One benefit of this SEUSS latch is that it can be fabricated in any modern integrated circuit process that provides complementary transistors. Another benefit is that scaling is not required to make the design functional. Logically, this invention is very flexible. When it is configured as an SEU tolerant SR latch, it can be converted into any known type of latch (SR latch, D latch, T flip flop, JK flip flop, etc.) with the addition of external logic. The SEU tolerance of the invention is not affected by any external logic that may be added.

Potential Applications: The SEUSS technology can be set or reset either synchronously or asynchronously; therefore, redundant circuitry can be added to the invention to increase its SEU tolerance.

This tech is also deployable in commercial products in niche applications where extreme design flexibility is paramount.

Contact: For more information about Fermilab’s SEUSS technology, contact Aaron Sauers at asauers@fnal.gov.

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